/*
 * File   : mac_top.v
 * Date   : 20171106
 * Author : Bibo Yang, rspwfpgas@163.com
 *
 */

`timescale 1ns/1ns
module mac_top(
    input  wire          rst,
    input  wire          clk,
    
    input  wire          phy_giga_mode,
    
	// Tx streaming interface
    output wire         gen_en     ,  // multicycle timing control signal
    input  wire [31: 0] int_data_i ,
    input  wire         int_valid_i,
    input  wire         int_sop_i  ,
    input  wire         int_eop_i  ,
    input  wire [ 1: 0] int_mod_i  ,
    
	// Rx streaming interface
    output wire         par_en     ,  // multicycle timing control signal
    output wire [31: 0] int_data_o ,
    output wire         int_valid_o,
    output wire         int_sop_o  ,
    output wire         int_eop_o  ,
    output wire [ 1: 0] int_mod_o  ,

	// PHY GMII interface
    `ifdef ENABLE_INTERNAL_PHY
    input  wire          gmii_rxclk ,
    input  wire          gmii_rxctrl,
    input  wire [ 7: 0]  gmii_rxdata,
    output wire          gmii_txclk ,
    output wire          gmii_txctrl,
    output wire [ 7: 0]  gmii_txdata
    `else
    input  wire         rgmii_rxclk ,
    input  wire         rgmii_rxctrl,
    input  wire [ 3: 0] rgmii_rxdata,
    output wire         rgmii_txclk ,
    output wire         rgmii_txctrl,
    output wire [ 3: 0] rgmii_txdata
    `endif
    
);


`ifdef ENABLE_INTERNAL_PHY
`else
// gmii to rgmii converter
wire       gmii_txclk;
wire       gmii_txctrl;
wire [7:0] gmii_txdata;
`endif

tx_top tx_top_inst(
    .rst          (        rst  ),  //input  wire         
    .clk          (        clk  ),  //input  wire 
    
    .phy_giga_mode(phy_giga_mode),  //input  wire         
    .gen_en       (       gen_en),  //output reg          // multicycle timing control signal
    
    .int_data_i   (  int_data_i ),  //input  wire [31: 0] 
    .int_valid_i  (  int_valid_i),  //input  wire         
    .int_sop_i    (  int_sop_i  ),  //input  wire         
    .int_eop_i    (  int_eop_i  ),  //input  wire         
    .int_mod_i    (  int_mod_i  ),  //input  wire [ 1: 0]

    `ifdef ENABLE_INTERNAL_PHY 
    .gmii_txclk  ( gmii_txclk ),  //output wire         
    .gmii_txctrl ( gmii_txctrl),  //output wire         
    .gmii_txdata ( gmii_txdata)   //output wire [ 7: 0] 
    `else
    `ifdef ENABLE_GMII_SIGS
    .gmii_txclk  ( gmii_txclk ),  //input  wire         
    .gmii_txctrl ( gmii_txctrl),  //input  wire         
    .gmii_txdata ( gmii_txdata),  //input  wire [ 7: 0] 
    `endif
    .rgmii_txclk (rgmii_txclk ),  //output wire         
    .rgmii_txctrl(rgmii_txctrl),  //output wire         
    .rgmii_txdata(rgmii_txdata)   //output wire [ 3: 0] 
    `endif

);

`ifdef ENABLE_INTERNAL_PHY
`else
// rgmii to gmii converter
wire       gmii_rxclk ;
wire       gmii_rxctrl;
wire [7:0] gmii_rxdata;
`endif

rx_top rx_top_inst(
    .rst          (        rst  ),  //input         
    .clk          (        clk  ),  //input  wire
    
    .phy_giga_mode(phy_giga_mode),  //input 
    .par_en       ( par_en      ),  //output reg           // multicycle timing control signal
                                                            
    .int_data_o   ( int_data_o  ),  //output reg  [31: 0] 
    .int_valid_o  ( int_valid_o ),  //output reg          
    .int_sop_o    ( int_sop_o   ),  //output reg          
    .int_eop_o    ( int_eop_o   ),  //output reg          
    .int_mod_o    ( int_mod_o   ),  //output reg  [ 1: 0]

    `ifdef ENABLE_INTERNAL_PHY
    .gmii_rxclk  ( gmii_rxclk ),  //input  wire        
    .gmii_rxctrl ( gmii_rxctrl),  //input  wire        
    .gmii_rxdata ( gmii_rxdata)   //input  wire [ 7: 0]
    `else
    `ifdef ENABLE_GMII_SIGS
    .gmii_rxclk  ( gmii_rxclk ),  //output wire        
    .gmii_rxctrl ( gmii_rxctrl),  //output wire        
    .gmii_rxdata ( gmii_rxdata),  //output wire [ 7: 0]
    `endif
    .rgmii_rxclk (rgmii_rxclk ),  //input  wire        
    .rgmii_rxctrl(rgmii_rxctrl),  //input  wire        
    .rgmii_rxdata(rgmii_rxdata)   //input  wire [ 3: 0]
    `endif
  
);

//// RGMII loopback
//assign {rgmii_txclk, rgmii_txctrl, rgmii_txdata} = {rgmii_rxclk, rgmii_rxctrl, rgmii_rxdata};

//// GMII loopback
//assign {gmii_txclk, gmii_txctrl, gmii_txdata} = {gmii_rxclk, gmii_rxctrl, gmii_rxdata};

// streaming loopback
//assign {int_data_i, int_valid_i, int_sop_i, int_eop_i, int_mod_i} = {int_data_o, int_valid_o, int_sop_o, int_eop_o, int_mod_o};


endmodule
